1. Field of the Invention
The present invention relates to a semiconductor device more specifically to a MOS transistor having an SOI (Silicon On Insulator) structure.
2. Description of Related Art
In general, to increase the integration of semiconductor devices, the size of each of the elements in the semiconductor devices must be reduced. In particular, to reduce the size of a MOS transistor, the impurity concentration of the channel region in the MOS transistor must be increased. However, such a high concentration of impurities leads to a higher parasitic capacitance of the MOS transistor. Accordingly, the electric characteristics of the MOS transistor are degraded with reduction of the size of the MOS transistor, so it is required that a low operating voltage is applied to the MOS transistor to maintain the expected life span.
As described above, with the development of highly integrated circuits, there are various problems to be solved. In particular, there are many problems in decreasing electric power consumption and in increase of a operating speed. Also the DIBL(Drain Induced Barrier Lowering) effect which causes the electric field generated from the drain region to have influence upon the source region due to the shortage of the channel length, and the punch-through effect may increase the leakage current of the MOS transistor.
To solve the above problems,an SOI (Silicon On Insulator) structure is proposed as shown in FIG. 1. In this case, an insulating layer 12 which is called a buried oxide layer, is formed on a substrate II and then parasitic capacitance is reduced by the buried oxide layer. Accordingly, the operating speed of circuits are increased. However, it is difficult to transfer downward the heat occurred in the MOS transistors, because the thermal conductivity of silicon oxide layer is 1/100 times as low as silicon layer.
Therefore, it is a primary factor in decreasing the efficiency of the device in with the increase of the heat in the MOS transistor. In addition, the leakage current of the MOS transistor may be greatly increased, because the electric field generated from a drain 14 propagates to the buried oxide layer in the MOS transistor. These characteristics become worse with smaller size of the MOS transistor.
In FIG. 1, reference numeral 11 denotes a silicon wafer, 13 a source, 15 a channel region, 16 a gate oxide layer, 17 a gate electrode.
An ideal structure of the MOS transistor may be implemented, by forming three impurity regions different from one another in the channel beneath the gate oxide layer. That is, a low impurity concentration layer doped, for example, less than 1xc3x971016 ions/cm3 is formed up to a predetermined depth, for example, 300 xc3x85 from the gate oxide layer to increase mobility of electrons or holes and to increase the driving capacity of the MOS transistor. Subsequently, beneath the low impurity concentration layer, a high impurity concentration layer doped, for example, more than 1xc3x971017 ions/cm3 is abruptly formed to reduce the punch-through effect and the DIBL effect from being generated in the MOS transistor and, at a predetermined depth, for example, 1000 xc3x85 a low impurity concentration is maintained again to decrease the parasitic capacitance of the source/drain regions. However, it is difficult to embody such a MOS transistor because of the impurity diffusion at a high temperature required in forming an gate oxide layer. That is, although a lay-out for forming such an ideal MOS transistor is provided, the impurities in the higher impurity concentration layer are diffused into the lower impurity concentration layers, at the time of growing the gate oxide layer at a high temperature. As a result, parasitic capacitance is increased by the downward diffused impurities, the current driving capacity is decreased by upward diffused impurities.
Therefore, an object of the present invention is to provide MOS transistors capable of improving the thermal conduction characteristics and a method for fabricating the same.
Also, another object of the present invention is to provide MOS transistors capable of improving the punch-through and the DIBL effect caused by the electric field generated from the drain regions of the MOS transistors.
In accordance with an aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; a first insulating layer, a selected material layer and a second insulating layer orderly stacked on said semiconductor substrate; and a semiconductor layer formed on the second insulating layer for providing an active area where MOS transistors are formed, wherein, said material layer provides a path for emitting heat generated from said MOS transistors.
In accordance with another aspect of the present invention, there is provided method of fabricating a semiconductor device comprising the steps of: forming a first insulating layer on a first semiconductor substrate; forming a polysilicon layer on the first insulating layer; forming a second insulating layer on the polysilicon layer; adhering a second semiconductor substrate to the second insulating layer; leaving a part of one of the first and second semiconductor substrate by using chemical mechanical polishing recipe; forming a gate insulating layer and a gate electrode on the whole structure; and forming junctions by using implantation to a selected depth.